Datasheet

Enhanced Capture Timer (ECT)
Register Descriptions
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Read anytime. Write used in the clearing mechanism (set bits cause
corresponding bits to be cleared). Writing a zero will not affect current
status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or
a write into an output compare channel ($10–$1F) will cause the
corresponding channel flag CnF to be cleared.
C7F–C0F — Input Capture/Output Compare Channel ‘n’ Flag.
C0F can also be set by 16-bit Pulse Accumulator B (PACB).
C3F–C0F can also be set by 8-bit pulse accumulators PAC3–PAC0.
Main Timer
Interrupt Flag 2
(TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, write the bit to one.
Read anytime. Write used in clearing mechanism (set bits cause
corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR
register is set.
TOF — Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000.
This bit is cleared automatically by a write to the TFLG2 register with
bit 7 set. (See also TCRE control bit explanation.)
Register offset: $000F
Bit 7 6 5 4 3 2 1 Bit 0
TOF 0 0 0 0 0 0 0
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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