Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously.
If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT is
reset from $FFFF to $0000.
PR2, PR1, PR0 — Timer Prescaler Select
These three bits specify the number of ÷2 stages that are to be
inserted between the module clock and the main timer counter.
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
Main Timer
Interrupt Flag 1
(TFLG1)
TFLG1 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, write a one to the bit.
Use of the TFMOD bit in the ICSYS register ($2B) in conjunction with the
use of the ICOVW register ($2A) allows a timer interrupt to be generated
after capturing two values in the capture and holding registers instead of
generating an interrupt for every capture.
Table 58 Prescaler Selection
PR2 PR1 PR0 Prescale Factor
000 1
001 2
010 4
011 8
100 16
101 32
110 64
1 1 1 128
Register offset: $000E
Bit 7 6 5 4 3 2 1 Bit 0
C7F C6F C5F C4F C3F C2F C1F C0F
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...