Datasheet

Enhanced Capture Timer (ECT)
Register Descriptions
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Timer Interrupt
Enable Register
(TIE)
Read or write anytime.
The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status
register. If cleared, the corresponding flag is disabled from causing a
hardware interrupt. If set, the corresponding flag is enabled to cause a
interrupt.
C7I–C0I — Input Capture/Output Compare “x” Interrupt Enable
Timer System
Control Register 2
(TSCR2)
Read or write anytime.
TOI — Timer Overflow Interrupt Enable
1 = Hardware interrupt requested when TOF flag set
0 = Interrupt inhibited
TCRE — Timer Counter Reset Enable
This bit allows the timer counter to be reset by a successful output
compare 7 event. This mode of operation is similar to an up-counting
modulus counter.
1 = Counter reset by a successful output compare 7
0 = Counter reset inhibited and counter free runs
Register offset: $000C
Bit 7 6 5 4 3 2 1 Bit 0
C7I C6I C5I C4I C3I C2I C1I C0I
RESET: 0 0 0 0 0 0 0 0
Register offset: $000D
Bit 7 6 5 4 3 2 1 Bit 0
TOI 0 0 0 TCRE PR2 PR1 PR0
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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