Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Timer Control
Registers 3 and 4
(TCTL3, TCTL4)
Read or write anytime.
EDGnB, EDGnA — Input Capture Edge Control
These eight pairs of control bits configure the input capture edge
detector circuits.
The four pairs of control bits of TCTL4 also configure the 8 bit pulse
accumulators PAC0–3.
For 16-bit pulse accumulator PACB, EDGE0B & EDGE0A, control bits
of TCTL4 will decide the active edge.
Register offset: $000A
Bit 7 6 5 4 3 2 1 Bit 0
TCTL3 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
RESET: 0 0 0 0 0 0 0 0
Register offset: $000B
Bit 7 6 5 4 3 2 1 Bit 0
TCTL4 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
RESET: 0 0 0 0 0 0 0 0
Table 57 Edge Detector Circuit Configuration
EDGnB EDGnA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
11
Capture on any edge (rising or
falling)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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