Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
TFFCA — Timer Fast Flag Clear All
1 = For TFLG1($0E), a read from an input capture or a write to the
output compare channel ($10–$1F) causes the corresponding
channel flag, CnF, to be cleared. For TFLG2 ($0F), any access
to the TCNT register ($04, $05) clears the TOF flag. Any
access to the PACN3 and PACN2 registers ($22, $23) clears
the PAOVF and PAIF flags in the PAFLG register ($21). Any
access to the PACN1 and PACN0 registers ($24, $25) clears
the PBOVF flag in the PBFLG register ($31). This has the
advantage of eliminating software overhead in a separate clear
sequence. Extra care is required to avoid accidental flag
clearing due to unintended accesses.
0 = Allows the timer flag clearing to function normally.
Timer Toggle On
Overflow Register
1 (TTOV)
Read or write anytime.
TOVx — Toggle On Overflow Bits
TOVx toggles output compare pin on overflow. This feature only takes
effect when in output compare mode. When set, it takes precedence
over forced output compare but not channel 7 override events.
1 = Toggle output compare pin on overflow feature enabled
0 = Toggle output compare pin on overflow feature disabled
Register offset: $0007
Bit 7 6 5 4 3 2 1 0
TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
RESET 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...