Datasheet

Central Processing Unit (CPU)
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
ORAA # opr8i
ORAA opr8a
ORAA opr16a
ORAA oprx0_xysppc
ORAA oprx9 , xysppc
ORAA oprx16 , xysppc
ORAA [D, xysppc ]
ORAA [ oprx16 , xysppc ]
OR accumulator A; (A) | (M)⇒A or
(A) | imm⇒A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8A ii
9A dd
BA hh ll
AA xb
AA xb ff
AA xb ee ff
AA xb
AA xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
ORAB # opr8i
ORAB opr8a
ORAB opr16a
ORAB oprx0_xysppc
ORAB oprx9 , xysppc
ORAB oprx16 , xysppc
ORAB [D, xysppc ]
ORAB [ oprx16 , xysppc ]
OR accumulator B; (B) | (M)⇒B or
(B) | imm⇒B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CA ii
DA dd
FA hh ll
EA xb
EA xb ff
EA xb ee ff
EA xb
EA xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
ORCC # opr8i OR CCR; (CCR) | imm⇒CCR IMM 14 ii P
PSHA Push A; (SP)–1⇒SP; (A)⇒M
SP
INH 36 Os
PSHB Push B; (SP)–1⇒SP; (B)⇒M
SP
INH 37 Os
PSHC Push CCR; (SP)–1⇒SP; (CCR)⇒M
SP
INH 39 Os
PSHD Push D; (SP)–2⇒SP;
(A:B)⇒M
SP
:M
SP+1
INH 3B OS
PSHX Push X; (SP)–2⇒SP;
(X
H
:X
L
)⇒M
SP
:M
SP+1
INH 34 OS
PSHY Push Y; (SP)–2⇒SP;
(Y
H
:Y
L
)⇒M
SP
:M
SP+1
INH 35 OS
PULA Pull A; (M
SP
)⇒A; (SP)+1⇒SP INH 32 ufO
PULB Pull B; (M
SP
)⇒B; (SP)+1⇒SP INH 33 ufO
PULC Pull CCR; (M
SP
)⇒CCR; (SP)+1⇒SP INH 38 ufO
PULD Pull D; (M
SP
:M
SP+1
)⇒A:B;
(SP)+2⇒SP
INH 3A UfO
PULX Pull X; (M
SP
:M
SP+1
)⇒X
H
:X
L
;
(SP)+2⇒SP
INH 30 UfO
PULY Pull Y; (M
SP
:M
SP+1
)⇒Y
H
:Y
L
;
(SP)+2⇒SP
INH 31 UfO
REV Rule evaluation, unweighted; find
smallest rule input; store to rule
outputs unless fuzzy output is
already larger
Special 18 3A Orf(t^tx)O*
ff+Orft^**
*The t^tx loop is executed once for each element in the rule list. The ^ denotes a check for pending interrupt requests.
**These are additional cycles caused by an interrupt: ff is the exit sequence and Orft^ is the re-entry sequence.
REVW Rule evaluation, weighted; rule
weights optional; find smallest rule
input; store to rule outputs unless
fuzzy output is already larger
Special 18 3B ORf(t^Tx)O*
or
ORf(r^ffRf)O**
ffff+ORft^***
ffff+ORfr^****
*When weighting is not enabled, the t^Tx loop is executed once for each element in the rule list. The ^ denotes a check for pending interrupt requests.
**When weighting is enabled, the t^Tx loop is replaced by r^ffRf.
***These are additional cycles caused by an interrupt when weighting is not enabled: ffff is the exit sequence and ORft^ is the re-entry sequence.
**** These are additional cycles caused by an interrupt when weighting is enabled: ffff is the exit sequence and ORfr^ is the re-entry sequence.
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
––––∆∆0–
––––∆∆0–
⇑
–
⇑⇑⇑⇑⇑⇑
––––––––
––––––––
––––––––
––––––––
––––––––
––––––––
––––––––
––––––––
∆
⇓
∆∆∆∆∆∆
––––––––
––––––––
––––––––
––?–??∆ ?
––?–??∆ !
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