Datasheet

Enhanced Capture Timer (ECT)
Register Descriptions
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Timer System
Control Register 1
(TSCR1)
Read or write anytime.
TEN — Timer Enable
1 = Allows the timer to function normally.
0 = Disables the main timer, including the counter. Can be used for
reducing power consumption.
If for any reason the timer is not active, there is no ÷64 clock for the
pulse accumulator since the ÷64 is generated by the timer prescaler.
TSWAI — Timer Module Stops While in Wait
1 = Disables the timer module when the MCU is in the wait mode.
Timer interrupts cannot be used to get the MCU out of wait.
0 = Allows the timer module to continue running during wait.
TSWAI also affects pulse accumulators and modulus down counters.
TSFRZ — Timer and Modulus Counter Stop While in Freeze Mode
1 = Disables the timer and modulus counter whenever the MCU is
in freeze mode. This is useful for emulation.
0 = Allows the timer and modulus counter to continue running while
in freeze mode.
TSFRZ does not stop the pulse accumulator.
Register offset: $0006
Bit 7 6 5 4 3 2 1 Bit 0
TEN TSWAI TSFRZ TFFCA
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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