Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Output Compare 7
Data Register
(OC7D)
Read or write anytime.
A channel 7 output compare can cause bits in the output compare 7 data
register to transfer to the timer port data register depending on the output
compare 7 mask register.
Timer Count
Register (TCNT)
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
Read anytime.
Write has no meaning or effect in the normal mode; only writable in
special modes (test_mode = 1).
The period of the first count after a write to the TCNT registers may be a
different size because the write is not synchronized with the prescaler
clock.
Register offset: $0003
Bit 7 6 5 4 3 2 1 Bit 0
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
RESET: 0 0 0 0 0 0 0 0
Register offset: $0004–$0005
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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