Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Register Descriptions
This section consists of register descriptions in address order. Each
description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register
diagrams, in bit order.
Timer Input
Capture/Output
Compare Select
(TIOS)
Read or write anytime.
IOS[7:0] — Input Capture or Output Compare Channel Configuration
1 = The corresponding channel acts as an output compare.
0 = The corresponding channel acts as an input capture
Timer Compare
Force Register
(CFORC)
Read anytime but will always return $00 (1 state is transient). Write
anytime.
FOC[7:0] — Force Output Compare Action for Channel 7–0
A write to this register with the corresponding data bit(s) set causes
the action which is programmed for output compare ‘n’ to occur
Register offset: $0000
Bit 7 6 5 4 3 2 1 Bit 0
IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
RESET: 0 0 0 0 0 0 0 0
Register offset: $0001
Bit 7 6 5 4 3 2 1 Bit 0
FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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