Datasheet

Enhanced Capture Timer (ECT)
Module Memory Map
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
IModule Specific
Signals
Figure 61 summarizes the ect_16b8c signal characteristics.
ect_oc_obe[7:0] These signals are the output buffer enable.When asserted, then pad is
driven by the timer outputs. When negated the timer outputs do not drive
the pad.
ect_oc_do[7:0] These signals are the output data from the module to the pads.
ect_ic_ind[7:0] Input digital from input buffer to module.
Module Memory Map
The memory map for the ECT module is given below in Table 55. The
Address listed for each register is the address offset. The total address
for each register is the sum of the base address for the ECT module and
the address offset for each register.
Figure 61 ECT16b8c Signal Characteristics
Signal Name Mnemonic
Input/
Output
Active
State
Reset
State
Function
Pad Input Signals
Timer Input Data ect_ic_ind[7:0] Input — — Input digital from buffer to module
Pad Control Signals
Output buffer enable ect_oc_obe[7:0] Output High 8’h00
When asserted the pad output is driven
by the timer outputs
Output Signals
Timer Output Data ect_oc_do[7:0] Output — — Output data from the module to the pads
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Freescale Semiconductor, Inc.
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