Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Signal Descriptions
Figure 60 ECT16b8c Block Interface
ECT16b8c
wdata[15:0]
rdata[15:0]
addr[5:1]
byte_15_8
byte_7_0
rwb
ectmcufi_int
test_access
clk
IPbus Interface
Pad / Pin Interface
ectpabo_int
ectpaai_int
ectpaao_int
ectovi_int
hard_async_reset_b
supervisor_access
ectch_int[7:0]
wait
ect_oc_obe[7:0]
ect_oc_do[7:0]
ect_ic_ind[7:0]
freeze
ipt_scan_mode
module_en
clk
Address
and Data
Buses
Protocol
Signals
Interrupt
Signals
Mode
Signals
Clocks
and
Resets
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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