Datasheet

Central Processing Unit (CPU)
Instruction Set Summary
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
LSRD Logical shift right D INH 49 O
MAXA
oprx0_xysppc
MAXA oprx9 , xysppc
MAXA oprx16 , xysppc
MAXA [D, xysppc ]
MAXA [ oprx16 , xysppc ]
Maximum in A: put larger of 2 unsigned
8-bit values in A; MAX[(A), (M)]⇒A;
N, Z, V, C bits reflect result of internal
compare [(A)–(M)]
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 18 xb
18 18 xb ff
18 18 xb ee ff
18 18 xb
18 18 xb ee ff
OrPf
OrPO
OfrPP
OfIfrPf
OfIPrPf
MAXM oprx0_xysppc
MAXM oprx9 , xysppc
MAXM oprx16 , xysppc
MAXM [D, xysppc ]
MAXM [ oprx16 , xysppc ]
Maximum in M; put larger of 2 unsigned
8-bit values in M; MAX[(A), (M)]⇒M;
N, Z, V, C bits reflect result of internal
compare [(A)–(M)]
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1C xb
18 1C xb ff
18 1C xb ee ff
18 1C xb
18 1C xb ee ff
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
MEM Determine grade of membership;
µ (grade)⇒M
Y
; (X)+4⇒X; (Y)+1⇒Y;
if (A)<P1 or (A)>P2 then µ=0, else µ=
MIN[((A)–P1)×S1, (P2–(A))×S2, $FF];
(A)=current crisp input value; X
points at 4-byte data describing
trapezoidal membership function
(P1, P2, S1, S2); X points at fuzzy
input (RAM location)
Special 01 RRfOw
MINA
oprx0_xysppc
MINA oprx9 , xysppc
MINA oprx16 , xysppc
MINA [D, xysppc ]
MINA [ oprx16 , xysppc ]
Minimum in A; put smaller of 2
unsigned 8-bit values in A;
MIN[(A), (M)]⇒A; N, Z, V, C bits
reflect result of internal compare
[(A)–(M)]
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 19 xb
18 19 xb ff
18 19 xb ee ff
18 19 xb
18 19 xb ee ff
OrPf
OrPO
OfrPP
OfIfrPf
OfIPrPf
MINM oprx0_xysppc
MINM oprx9 , xysppc
MINM oprx16 , xysppc
MINM [D, xysppc ]
MINM [ oprx16 , xysppc ]
Minimum in N; put smaller of 2
unsigned 8-bit values
in M; MIN[(A), (M)]⇒M; N, Z, V, C bits
reflect result of internal compare
[(A)–(M)]
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1D xb
18 1D xb ff
18 1D xb ee ff
18 1D xb
18 1D xb ee ff
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
MOVB # opr8 , opr16a
MOVB # opr8i , oprx0_xysppc
MOVB opr16a , opr16a
MOVB opr16a , oprx0_xysppc
MOVB oprx0_xysppc , opr16a
MOVB oprx0_xysppc , oprx0_xysppc
Move byte; memory-to-memory 8-bit
byte-move; (M
1
)⇒M
2
; first operand
specifies byte to move
IMM-EXT
IMM-IDX
EXT-EXT
EXT-IDX
IDX-EXT
IDX-IDX
18 0B ii hh ll
18 08 xb ii
18 0C hh ll hh ll
18 09 xb hh ll
18 0D xb hh ll
18 0A xb xb
OPwP
OPwO
OrPwPO
OPrPw
OrPwP
OrPwO
MOVW #
oprx16 , opr16a
MOVW # opr16i , oprx0_xysppc
MOVW opr16a , opr16a
MOVW opr16a , oprx0_xysppc
MOVW oprx0_xysppc , opr16a
MOVW oprx0_xysppc , oprx0_xysppc
Move word; memory-to-memory
16-bit word-move;
(M
1
:M
1
+1)⇒M
2
:M
2
+1; first operand
specifies word to move
IMM-EXT
IMM-IDX
EXT-EXT
EXT-IDX
IDX-EXT
IDX-IDX
18 03 jj kk hh ll
18 00 xb jj kk
18 04 hh ll hh ll
18 01 xb hh ll
18 05 xb hh ll
18 02 xb xb
OPWPO
OPPW
ORPWPO
OPRPW
ORPWP
ORPWO
MUL Multiply, unsigned, 8 by 8-bit;
(A)×(B)⇒A:B
INH 12 O
NEG opr16a
NEG oprx0_xysppc
NEG oprx9 , xysppc
NEG oprx16 , xysppc
NEG [D, xysppc ]
NEG [ oprx16 , xysppc ]
NEGA
NEGB
Negate M; 0–(M)⇒M or (M)+1⇒M
Negate A; 0–(A)⇒A or (A)+1⇒A
Negate B; 0–(B)⇒B or (B)+1⇒B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
70 hh ll
60 xb
60 xb ff
60 xb ee ff
60 xb
60 xb ee ff
40
50
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
NOP No operation INH A7 O
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
Cb7 b0ABb7b0
0
––––0∆∆∆
––––∆∆∆∆
––––∆∆∆∆
––?–????
––––∆∆∆∆
––––∆∆∆∆
––––––––
––––––––
–––––––∆
––––∆∆∆∆
––––––––
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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