Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Enhanced Capture Timer (ECT)
Block Diagram
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Figure 56 16-Bit Pulse Accumulators Block Diagram
Edge detector
8-bit PAC2
Intermodule Bus
8-bit PAC3
PT7
PT0
M clock
Divide by 64
Clock select
CLK0
CLK1
4:1 MUX
TIMCLK
PACLK
PACLK / 256
PACLK / 65536
Prescaled clock
(PCLK)
(Timer clock)
Interrupt
MUX
(PAMOD)
Edge detector
PAC A
Delay counter
(PACN3) (PACN2)
8-bit PAC08-bit PAC1
Interrupt
PAC B
(PACN1) (PACN0)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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