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Enhanced Capture Timer (ECT)
Block Diagram
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Figure 56 16-Bit Pulse Accumulators Block Diagram
Edge detector
8-bit PAC2
Intermodule Bus
8-bit PAC3
PT7
PT0
M clock
Divide by 64
Clock select
CLK0
CLK1
4:1 MUX
TIMCLK
PACLK
PACLK / 256
PACLK / 65536
Prescaled clock
(PCLK)
(Timer clock)
Interrupt
MUX
(PAMOD)
Edge detector
PAC A
Delay counter
(PACN3) (PACN2)
8-bit PAC08-bit PAC1
Interrupt
PAC B
(PACN1) (PACN0)
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