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Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Figure 55 8-Bit Pulse Accumulators Block Diagram
IP data bus
PT0
Load holding register and reset pulse accumulator
0
0
EDG3
EDG2
EDG1
EDG0
Edge detector Delay counter
Interrupt
Interrupt
PT1
Edge detector
Delay counter
PT2
Edge detector
Delay counter
PT3
Edge detector
Delay counter
8-bit PAC0 (PACN0)
PA0H holding register
0
8-bit PAC1 (PACN1)
PA1H holding register
0
8-bit PAC2 (PACN2)
PA2H holding register
0
8-bit PAC3 (PACN3)
PA3H holding register
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