Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Figure 55 8-Bit Pulse Accumulators Block Diagram
IP data bus
PT0
Load holding register and reset pulse accumulator
0
0
EDG3
EDG2
EDG1
EDG0
Edge detector Delay counter
Interrupt
Interrupt
PT1
Edge detector
Delay counter
PT2
Edge detector
Delay counter
PT3
Edge detector
Delay counter
8-bit PAC0 (PACN0)
PA0H holding register
0
8-bit PAC1 (PACN1)
PA1H holding register
0
8-bit PAC2 (PACN2)
PA2H holding register
0
8-bit PAC3 (PACN3)
PA3H holding register
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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