Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
byte and low byte separately for all of these registers may not yield the
same result as accessing them in one word.
Features
• 16-Bit Buffer Register for four Input Capture (IC) channels.
• Four 8-Bit Pulse Accumulators with 8-bit buffer registers
associated with the four buffered IC channels. Configurable also
as two 16-Bit Pulse Accumulators.
• 16-Bit Modulus Down-Counter with 4-bit Prescaler.
• Four user selectable Delay Counters for input noise immunity
increase.
• Support for only 16-bit access on the IP bus.
Modes of Operation
STOP: Timer and modulus counter are off since clocks are
stopped.
FREEZE: Timer and modulus counter keep on running, unless
TSFRZ in TSCR($06) is set to one.
WAIT: Counters keep on running, unless TSWAI in TSCR ($06)
is set to one.
NORMAL: Timer and modulus counter keep on running, unless TEN
in TSCR($06) respectively MCEN in MCCTL ($26) are
cleared.
Abbreviations
Following abbreviations are used in the document.
M clock – Module clock (clk of IPbus)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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