Datasheet

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
Low Power Options
This section summarizes the low power options available in the PWM
module. Low power design practices are implemented where possible.
The IP bus module clock (ipb_clk) is used for the programming model
register writes. This clock is active only when module_en is asserted.
Run Mode While in run mode, if all eight PWM channels are disabled
(PWME7–0=0), the prescaler counter shuts off for power savings (see
Figure 46).
Wait Mode The PWM will keep running in WAIT unless the PSWAI bit in the
PWMCTL register is enabled. This allows for lower power consumption
in WAIT mode by disabling the input clock to the prescaler. When in
WAIT mode with this bit set, no activity in the PWM occurs and the PWM
outputs go to a static state (high or low).
Stop Mode In STOP mode, the PWM module is stopped since all the clocks from IP
bus to the module are stopped. The PWM outputs go to a static state
(high or low).
Interrupt Operation
The PWM module has only one interrupt which is generated at the time
of emergency shutdown, if the corresponding enable bit (PWMIE in the
PWMSDN register) is set.
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Freescale Semiconductor, Inc.
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