Datasheet

Central Processing Unit (CPU)
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
LDD # opr16i
LDD opr8a
LDD opr16a
LDD oprx0_xysppc
LDD oprx9 , xysppc
LDD oprx16 , xysppc
LDD [D, xysppc ]
LDD [ oprx16 , xysppc ]
Load D; (M:M+1)⇒A:B or imm⇒A:B IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CC jj kk
DC dd
FC hh ll
EC xb
EC xb ff
EC xb ee ff
EC xb
EC xb ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
LDS # opr16i
LDS opr8a
LDS opr16a
LDS oprx0_xysppc
LDS oprx9 , xysppc
LDS oprx16 , xysppc
LDS [D, xysppc ]
LDS [ oprx16 , xysppc ]
Load SP; (M:M+1)⇒SP or imm⇒SP IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CF jj kk
DF dd
FF hh ll
EF xb
EF xb ff
EF xb ee ff
EF xb
EF xb ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
LDX # opr16i
LDX opr8a
LDX opr16a
LDX oprx0_xysppc
LDX oprx9 , xysppc
LDX oprx16 , xysppc
LDX [D, xysppc ]
LDX [ oprx16 , xysppc ]
Load X; (M:M+1)⇒X or imm⇒X IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CE jj kk
DE dd
FE hh ll
EE xb
EE xb ff
EE xb ee ff
EE xb
EE xb ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
LDY #
opr16i
LDY opr8a
LDY opr16a
LDY oprx0_xysppc
LDY oprx9 , xysppc
LDY oprx16 , xysppc
LDY [D, xysppc ]
LDY [ oprx16 , xysppc ]
Load Y; (M:M+1)⇒Y or imm⇒Y IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CD jj kk
DD dd
FD hh ll
ED xb
ED xb ff
ED xb ee ff
ED xb
ED xb ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
LEAS oprx0_xysppc
LEAS oprx9 , xysppc
LEAS oprx16 , xysppc
Load effective address into SP;
effective address⇒SP
IDX
IDX1
IDX2
1B xb
1B xb ff
1B xb ee ff
Pf
PO
PP
LEAX oprx0_xysppc
LEAX oprx9 , xysppc
LEAX oprx16 , xysppc
Load effective address into X;
effective address⇒X
IDX
IDX1
IDX2
1A xb
1A xb ff
1A xb ee ff
Pf
PO
PP
LEAY oprx0_xysppc
LEAY oprx9 , xysppc
LEAY oprx16 , xysppc
Load effective address into Y;
effective address⇒Y
IDX
IDX1
IDX2
19 xb
19 xb ff
19 xb ee ff
Pf
PO
PP
LSL opr16a
LSL oprx0_xysppc
LSL oprx9 , xysppc
LSL oprx16 , xysppc
LSL [D, xysppc ]
LSL [ oprx16 , xysppc ]
LSLA
LSLB
Logical shift left M; same as ASL
Logical shift left A; same as ASLA
Logical shift left B; same as ASLB
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
78 hh ll
68 xb
68 xb ff
68 xb ee ff
68 xb
68 xb ee ff
48
58
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
LSLD Logical shift left D; same as ASLD INH 59 O
LSR
opr16a
LSR oprx0_xysppc
LSR oprx9 , xysppc
LSR oprx16 , xysppc
LSR [D, xysppc ]
LSR [ oprx16 , xysppc ]
LSRA
LSRB
Logical shift right M
Logical shift right A
Logical shift right B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
74 hh ll
64 xb
64 xb ff
64 xb ee ff
64 xb
64 xb ee ff
44
54
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
––––∆∆0–
––––∆∆0–
––––∆∆0–
––––∆∆0–
––––––––
––––––––
– – – – – – – –
C
0
b7
b0
––––∆∆∆∆
C
0
b7 b0ABb7b0
––––∆∆∆∆
C
0
b7
b0
––––0∆∆∆
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