Datasheet

Pulse Width Modulator (PWM)
Functional Description
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
channels 4 and 5 are concatenated, channel 3 when channels 2 and 3
are concatenated, and channel 1 when channels 0 and 1 are
concatenated. The resulting PWM is output to the pins of the
corresponding low order 8-bit channel as also shown in Figure 52. The
polarity of the resulting PWM output is controlled by the PPOLx bit of the
corresponding low order 8-bit channel as well.
Once concatenated mode is enabled (CONxx bits set in PWMCTL
register) then enabling/disabling the corresponding 16-bit PWM channel
is controlled by the low order PWMEx bit. In this case, the high order
bytes PWMEx bits have no effect and their corresponding PWM output
is disabled.
In concatenated mode, writes to the 16-bit counter by using a 16-bit
access or writes to either the low or high order byte of the counter will
reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
Either left aligned or center aligned output mode can be used in
concatenated mode and is controlled by the low order CAEx bit. The
high order CAEx bit has no effect.
The table shown below is used to summarize which channels are used
to set the various control bits when in 16-bit mode.
Table 53 16-bit Concatenation Mode Summary
CONxx PWMEx PPOLx PCLKx CAEx
PWMx
OUTPUT
CON67 PWME7 PPOL7 PCLK7 CAE7 PWM7
CON45 PWME5 PPOL5 PCLK5 CAE5 PWM5
CON23 PWME3 PPOL3 PCLK3 CAE3 PWM3
CON01 PWME1 PPOL1 PCLK1 CAE1 PWM1
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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