Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
Figure 52 PWM 16-Bit Mode
When using the 16-bit concatenated mode, the clock source is
determined by the low order 8-bit channel clock select control bits. That
is channel 7 when channels 6 and 7 are concatenated, channel 5 when
PWMCNT6 PWCNT7
PWM7
Clock Source 7
High Low
Period/Duty Compare
PWMCNT4 PWCNT5
PWM5
Clock Source 5
High Low
Period/Duty Compare
PWMCNT2 PWCNT3
PWM3
Clock Source 3
High Low
Period/Duty Compare
PWMCNT0 PWCNT1
PWM1
Clock Source 1
High Low
Period/Duty Compare
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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