Datasheet

Pulse Width Modulator (PWM)
Functional Description
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
Figure 49 PWM Left Aligned Output Example Waveform
Center Aligned
Outputs
For Center Aligned Output Mode selection, set the CAEx bit (CAEx=1)
in the PWMCAE register and the corresponding PWM output will be
center aligned.
The 8-bit counter operates as an up/down counter in this mode and is
set to up whenever the counter is equal to $00. The counter compares
to two registers, a duty register and a period register as shown in the
block diagram in Figure 47. When the PWM counter matches the duty
register the output flip-flop changes state causing the PWM waveform to
also change state. A match between the PWM counter and the period
register changes the counter direction from an up-count to a
down-count. When the PWM counter decrements and matches the duty
register again, the output flip-flop changes state causing the PWM
output to also change state. When the PWM counter decrements and
reaches zero, the counter direction changes from a down-count back to
an up-count and a load from the double buffer period and duty registers
to the associated registers is performed as described in PWM Period
and Duty. The counter counts from 0 up to the value in the period register
and then back down to 0. Thus the effective period is PWMPERx*2.
NOTE: Changing the PWM output mode from Left Aligned Output to Center
Aligned Output (or vice versa) while channels are operating can cause
irregularities in the PWM output. It is recommended to program the
output mode before enabling the PWM channel.
PERIOD = 400ns
E=100ns
DUTY CYCLE = 75%
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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