Datasheet

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
Figure 48 PWM Left Aligned Output Waveform
To calculate the output frequency in left aligned output mode for a
particular channel, take the selected clock source frequency for the
channel (A, B, SA, or SB) and divide it by the value in the period register
for that channel.
• PWMx Frequency = Clock(A, B, SA, or SB) / PWMPERx
• PWMx Duty Cycle (high time as a % of period):
– Polarity = 0 (PPOLx=0)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
– Polarity = 1 (PPOLx=1)
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
As an example of a left aligned output, consider the following case:
Clock Source = E, where E=10MHz (100ns period)
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
PWMx Frequency = 10MHz/4 = 2.5MHz
PWMx Period = 400ns
PWMx Duty Cycle = 3/4 *100% = 75%
The output waveform generated is shown in Figure 49.
PWMDTYx
Period = PWMPERx
PPOLx=0
PPOLx=1
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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