Datasheet

Pulse Width Modulator (PWM)
Functional Description
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
The counter is cleared at the end of the effective period (see Left Aligned
Outputs and Center Aligned Outputs for more details).
Left Aligned
Outputs
The PWM timer provides the choice of two types of outputs, Left Aligned
or Center Aligned outputs. They are selected with the CAEx bits in the
PWMCAE register. If the CAEx bit is cleared (CAEx=0), the
corresponding PWM output will be left aligned.
In left aligned output mode, the 8-bit counter is configured as an up
counter only. It compares to two registers, a duty register and a period
register as shown in the block diagram in Figure 47. When the PWM
counter matches the duty register the output flip-flop changes state
causing the PWM waveform to also change state. A match between the
PWM counter and the period register resets the counter and the output
flip-flop as shown in Figure 47 as well as performing a load from the
double buffer period and duty register to the associated registers as
described in PWM Period and Duty. The counter counts from 0 to the
value in the period register – 1.
NOTE: Changing the PWM output mode from Left Aligned Output to Center
Aligned Output (or vice versa) while channels are operating can cause
irregularities in the PWM output. It is recommended to program the
output mode before enabling the PWM channel.
Table 52 PWM Timer Counter Conditions
Counter Clears ($00) Counter Counts Counter Stops
When PWMCNTx register written
to any value
When PWM channel is enabled
(PWMEx=1). Counts from last
value in PWMCNTx.
When PWM channel is disabled
(PWMEx=0)
Effective period ends
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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