Datasheet

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
PWM Timer
Counters
Each channel has a dedicated 8-bit up/down counter which runs at the
rate of the selected clock source (reference PWM Clock Select for the
available clock sources and rates). The counter compares to two
registers, a duty register and a period register as shown in Figure 47.
When the PWM counter matches the duty register the output flip-flop
changes state causing the PWM waveform to also change state. A
match between the PWM counter and the period register behaves
differently depending on what output mode is selected as shown in
Figure 47 and described in Left Aligned Outputs and Center Aligned
Outputs.
Each channel counter can be read at anytime without affecting the count
or the operation of the PWM channel.
Any value written to the counter causes the counter to reset to $00, the
counter direction to be set to up, the immediate load of both duty and
period registers with values from the buffers, and the output to change
according to the polarity bit. When the channel is disabled (PWMEx=0),
the counter stops. When a channel becomes enabled (PWMEx=1), the
associated PWM counter continues from the count in the PWMCNTx
register. This allows the waveform to continue where it left off when the
channel is re-enabled. When the channel is disabled, writing ‘0’ to the
period register will cause the counter to reset on the next selected clock.
NOTE: If the user wants to start a new ‘clean’ PWM waveform without any
‘history’ from the old waveform, the user must write to channel counter
(PWMCNTx) prior to enabling the PWM channel (PWMEx=1).
Generally, writes to the counter are done prior to enabling a channel in
order to start from a known state. However, writing a counter can also be
done while the PWM channel is enabled (counting). The effect is similar
to writing the counter when the channel is disabled except that the new
period is started immediately with the output set according to the polarity
bit.
CAUTION: Writing to the counter while the channel is enabled can cause an
irregular PWM cycle to occur.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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