Datasheet

Central Processing Unit (CPU)
Instruction Set Summary
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
LBCS rel16 Long branch if C set; if C=1, then
(PC)+4+rel⇒PC; same as LBLO
REL 18 25 qq rr OPPP (branch)
OPO (no branch)
LBEQ rel16 Long branch if equal; if Z=1, then
(PC)+4+rel⇒PC
REL 18 27 qq rr OPPP (branch)
OPO (no branch)
LBGE rel16 Long branch if ≥ 0, signed; if N⊕V=0,
then (PC)+4+rel⇒PC
REL 18 2C qq rr OPPP (branch)
OPO (no branch)
LBGT rel16 Long branch if > 0, signed; if
Z | (N⊕V)=0, then (PC)+4+rel⇒PC
REL 18 2E qq rr OPPP (branch)
OPO (no branch)
LBHI rel16 Long branch if higher, unsigned; if
C | Z=0, then (PC)+4+rel⇒PC
REL 18 22 qq rr OPPP (branch)
OPO (no branch)
LBHS rel16 Long branch if higher or same,
unsigned; if C=0, then
(PC)+4+rel⇒PC; same as LBCC
REL 18 24 qq rr OPPP (branch)
OPO (no branch)
LBLE rel16 Long branch if ≤ 0, signed; if
Z | (N⊕V)=1, then (PC)+4+rel⇒PC
REL 18 2F qq rr OPPP (branch)
OPO (no branch)
LBLO
rel16 Long branch if lower, unsigned; if C=1,
then (PC)+4+rel⇒PC; same as
LBCS
REL 18 25 qq rr OPPP (branch)
OPO (no branch)
LBLS rel16 Long branch if lower or same, unsigned;
if C | Z=1, then (PC)+4+rel⇒PC
REL 18 23 qq rr OPPP (branch)
OPO (no branch)
LBLT rel16 Long branch if < 0, signed; if N⊕V=1,
then (PC)+4+rel⇒PC
REL 18 2D qq rr OPPP (branch)
OPO (no branch)
LBMI rel16 Long branch if minus; if N=1, then
(PC)+4+rel⇒PC
REL 18 2B qq rr OPPP (branch)
OPO (no branch)
LBNE rel16 Long branch if not equal to 0; if Z=0,
then (PC)+4+rel⇒PC
REL 18 26 qq rr OPPP (branch)
OPO (no branch)
LBPL
rel16 Long branch if plus; if N=0, then
(PC)+4+rel⇒PC
REL 18 2A qq rr OPPP (branch)
OPO (no branch)
LBRA rel16 Long branch always REL 18 20 qq rr OPPP
LBRN rel16 Long branch never REL 18 21 qq rr OPO
LBVC
rel16 Long branch if V clear; if V=0, then
(PC)+4+rel⇒PC
REL 18 28 qq rr OPPP (branch)
OPO (no branch)
LBVS rel16 Long branch if V set; if V=1, then
(PC)+4+rel⇒PC
REL 18 29 qq rr OPPP (branch)
OPO (no branch)
LDAA # opr8i
LDAA opr8a
LDAA opr16a
LDAA oprx0_xysppc
LDAA oprx9 , xysppc
LDAA oprx16 , xysppc
LDAA [D, xysppc ]
LDAA [ oprx16 , xysppc ]
Load A; (M)⇒A or imm⇒A IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
86 ii
96 dd
B6 hh ll
A6 xb
A6 xb ff
A6 xb ee ff
A6 xb
A6 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
LDAB # opr8i
LDAB opr8a
LDAB opr16a
LDAB oprx0_xysppc
LDAB oprx9 , xysppc
LDAB oprx16 , xysppc
LDAB [D, xysppc ]
LDAB [ oprx16 , xysppc ]
Load B; (M)⇒B or imm⇒B IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C6 ii
D6 dd
F6 hh ll
E6 xb
E6 xb ff
E6 xb ee ff
E6 xb
E6 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
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Freescale Semiconductor, Inc.
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