Datasheet

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
Prescale The input clock to the PWM prescaler is the bus clock. It can be disabled
whenever the part is in freeze mode by setting the PFRZ bit in the
PWMCTL register. If this bit is set, whenever the MCU is in freeze mode
(ipg_freeze active) the input clock to the prescaler is disabled. This is
useful for emulation in order to freeze the PWM. The input clock can also
be disabled when all eight PWM channels are disabled (PWME7–0=0).
This is useful for reducing power by disabling the prescale counter.
Clock A and clock B are scaled values of the input clock. The value is
software selectable for both clock A and clock B and has options of E,
E/2, E/4, E/8, E/16, E/32, E/64, or E/128. The value selected for clock A
is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK
register. The value selected for clock B is determined by the PCKB2,
PCKB1, PCKB0 bits also in the PWMPRCLK register.
Clock Scale The scaled A clock uses clock A as an input and divides it further with a
user programmable value and then divides this by 2. The scaled B clock
uses clock B as an input and divides it further with a user programmable
value and then divides this by 2. The rates available for clock SA are
software selectable to be clock A divided by 2, 4, 6, 8, ..., or 512 in
increments of divide by 2. Similar rates are available for clock SB.
Clock A is used as an input to an 8-bit down counter. This down counter
loads a user programmable scale value from the scale register
(PWMSCLA). When the down counter reaches one, two things happen;
a pulse is output and the 8-bit counter is re-loaded. The output signal
from this circuit is further divided by two. This gives a greater range with
only a slight reduction in granularity. Clock SA equals Clock A divided by
two times the value in the PWMSCLA register.
NOTE: Clock SA = Clock A / (2 * PWMSCLA)
When PWMSCLA = $00, PWMSCLA value is considered a full scale
value of 256. Clock A is thus divided by 512.
Similarly, Clock B is used as an input to an 8-bit down counter followed
by a divide by two producing clock SB. Thus, clock SB equals Clock B
divided by two times the value in the PWMSCLB register.
NOTE: Clock SB = Clock B / (2 * PWMSCLB)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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