Datasheet

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
Functional Description
PWM Clock Select There are four available clocks called clock A, clock B, clock SA (Scaled
A), and clock SB (Scaled B). These four clocks are based on the clock,
E Clock which runs at the same frequency as the IP bus clock
ipg_clock .
NOTE: All E Clock (E) references within this document are used to refer only to
the frequency and do not suggest that this clock is actually used in
implementation.
For the MC9S12DP256, E clock is same as the ipg_clk. So all reference
to E clock in this document are to be read as ipg_clk.
Clock A and B can be software selected to be E, E/2, E/4, E/8,..., E/64,
E/128. Clock SA uses clock A as an input and divides it further with a
reloadable counter. Similarly, Clock SB uses clock B as an input and
divides it further with a reloadable counter. The rates available for clock
SA are software selectable to be clock A divided by 2, 4, 6, 8, ..., or 512
in increments of divide by 2. Similar rates are available for clock SB.
Each PWM channel has the capability of selecting one of two clocks,
either the pre-scaled clock (clock A or B) or the scaled clock (clock SA
or SB).
The block diagram in Figure 46 shows the four different clocks and how
the scaled clocks are created.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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