Datasheet

Pulse Width Modulator (PWM)
Register Descriptions
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
PWMRSTRT — PWM Restart.
The PWM can only be restarted if the PWM channel input is
de-asserted. After writing a ‘1’ to the PWMRSTRT bit (trigger event)
the PWM channels start running after the corresponding counter
passes next ‘counter == 0’ phase.
Also if the PWM7ENA bit is reset to 0, the PWM do not start before
the counter passes $00.
The bit is always read as ‘0’.
PWMIE — PWM Interrupt Enable
If interrupt is enabled an interrupt to the CPU is asserted.
1 = PWM interrupt is enabled.
0 = PWM interrupt is disabled.
PWMIF — PWM Interrupt Flag
Any change from passive to asserted (active) state or from active to
passive state will be flagged by setting the PWMIF flag = 1. The flag
is cleared by writing a ‘1’ to it. Writing a ‘0’ has no effect.
1 = change on PWM7IN input
0 = No change on PWM7IN input.
Reserved Registers
Ð PWM Reserved
Memory Space
The following registers are reserved for PWM future expansion. Reading
any one of these locations returns $00. Writing any one of these
locations has no effect.
Read: will always read $00
Write: unimplemented
Address Offset: $0025, $0026, $0027
Bit 7 654321Bit 0
Read: 00000000
Write:
Reset: 00000000
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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