Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
PWM Shutdown
Register
(PWMSDN)
The PWMSDN register provides for the shutdown functionality of the
PWM module in the emergency cases.
Read: anytime
Write: anytime
PWM7ENA — PWM emergency shutdown Enable
If this bit is ‘1’ the pin associated with channel 7 is forced to input and
the emergency shutdown feature is enabled.All the other bits in this
register are meaningful only if PWM7ENA = 1.
1 = PWM emergency feature is enabled.
0 = PWM emergency feature disabled.
PWM7INL — PWM shutdown active input level for ch. 7.
If the emergency shutdown feature is enabled (PWM7ENA = 1), this
bit determines the active level of the PWM7channel.
1 = Active level is high
0 = Active level is low
PWM7IN — PWM channel 7 input status.
This reflects the current status of the PWM7 pin.
PWMLVL — PWM shutdown output Level.
If active level as defined by the PWM7IN input, gets asserted all
enabled PWM channels are immediately driven to the level defined by
PWMLVL.
1 = PWM outputs are forced to 1.
0 = PWM outputs are forced to 0
Address Offset: $0024
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PWMIF PWMIE
0
PWMLVL
0 PWM7IN
PWM7INL PWM7ENA
Write: PWMRSTRT
Reset: 0 0 0 0 0 0 0 0
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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