Datasheet

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
PWM Channel
Duty Registers
(PWMDTYx)
There is a dedicated duty register for each channel. The value in this
register determines the duty of the associated PWM channel. The duty
value is compared to the counter and if it is equal to the counter value a
match occurs and the output changes state.
The duty registers for each channel are double buffered so that if they
change while the channel is enabled, the change will NOT take effect
until one of the following occurs:
• The effective period ends
• The counter is written (counter resets to $00)
• The channel is disabled
In this way, the output of the PWM will always be either the old duty
waveform or the new duty waveform, not some variation in between. If
the channel is not enabled, then writes to the duty register will go directly
to the latches as well as the buffer.
NOTE: Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active duty due to the double
buffering scheme.
Reference PWM Period and Duty for more information.
NOTE: Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time. If the polarity bit is one, the output
starts high and then goes low when the duty count is reached, so the
duty registers contain a count of the high time. If the polarity bit is zero,
the output starts low and then goes high when the duty count is reached,
so the duty registers contain a count of the low time.
To calculate the output duty cycle (high time as a % of period) for a
particular channel:
• Polarity = 0 (PPOLx=0)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
• Polarity = 1 (PPOLx=1)
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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