Datasheet

Central Processing Unit (CPU)
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
EORB # opr8i
EORB opr8a
EORB opr16a
EORB oprx0_xysppc
EORB oprx9 , xysppc
EORB oprx16 , xysppc
EORB [D, xysppc ]
EORB [ oprx16 , xysppc ]
Exclusive OR B; (B)⊕(M)⇒B or
(B)⊕imm⇒B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C8 ii
D8 dd
F8 hh ll
E8 xb
E8 xb ff
E8 xb ee ff
E8 xb
E8 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
ETBL oprx0_xysppc Extended table lookup and interpolate,
16-bit; (M:M+1)+[(B)×
((M+2:M+3)–(M:M+1))]⇒D
IDX 18 3F xb ORRffffffP
Before executing ETBL, initialize B with fractional part of lookup value; initialize index register to point to first table entry (M:M+1). No extensions or
indirect addressing allowed.
EXG abcdxysp , abcdxysp Exchange register contents;
(r1)⇔(r2); r1 and r2 same size or
$00:(r1)⇒r2; r1=8-bit; r2=16-bit or
(r1
L
)⇔(r2); r1=16-bit; r2=8-bit
INH B7 eb P
FDIV Fractional divide; 16 by 16-bit;
(D)÷(X)⇒X; remainder⇒D
INH 18 11 OffffffffffO
IBEQ
abdxysp , rel9 Increment and branch if equal to 0;
(counter)+1⇒counter;
if (counter)=0, then branch
REL
(9-bit)
04 lb rr PPP (branch)
PPO (no branch)
IBNE abdxysp , rel9 Increment and branch if not equal to 0;
(counter)+1⇒counter;
if (counter)≠0, then branch
REL
(9-bit)
04 lb rr PPP (branch)
PPO (no branch)
IDIV Integer divide, unsigned; 16 by 16-bit;
(D)÷(X)⇒X; remainder⇒D
INH 18 10 OffffffffffO
IDIVS Integer divide, signed; 16 by 16-bit;
(D)÷(X)⇒X; remainder⇒D
INH 18 15 OffffffffffO
INC opr16a
INC oprx0_xysppc
INC oprx9 , xysppc
INC oprx16 , xysppc
INC [D, xysppc ]
INC [ oprx16 , xysppc ]
INCA
INCB
Increment M; (M)+1⇒M
Increment A; (A)+1⇒A
Increment B; (B)+1⇒B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
72 hh ll
62 xb
62 xb ff
62 xb ee ff
62 xb
62 xb ee ff
42
52
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
INS Increment SP; (SP)+1⇒SP;
assembles as LEAS 1,SP
IDX 1B 81 Pf
INX Increment X; (X)+1⇒X INH 08 O
INY Increment Y; (Y)+1⇒Y INH 02 O
JMP
opr16a
JMP oprx0_xysppc
JMP oprx9 , xysppc
JMP oprx16 , xysppc
JMP [D, xysppc ]
JMP [ oprx16 , xysppc ]
Jump; subroutine address⇒PC EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
06 hh ll
05 xb
05 xb ff
05 xb ee ff
05 xb
05 xb ee ff
PPP
PPP
PPP
fPPP
fIfPPP
fIfPPP
JSR opr8a
JSR opr16a
JSR oprx0_xysppc
JSR oprx9 , xysppc
JSR oprx16 , xysppc
JSR [D, xysppc ]
JSR [ oprx16 , xysppc ]
Jump to subroutine; (SP)–2⇒SP;
RTN
H
:RTN
L
⇒M
SP
:M
SP+1
;
subroutine address⇒PC
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
17 dd
16 hh ll
15 xb
15 xb ff
15 xb ee ff
15 xb
15 xb ee ff
SPPP
SPPP
PPPS
PPPS
fPPPS
fIfPPPS
fIfPPPS
LBCC rel16 Long branch if C clear; if C=0, then
(PC)+4+rel⇒PC; same as LBHS
REL 18 24 qq rr OPPP (branch)
OPO (no branch)
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
––––∆∆0–
––––∆∆– ∆
––––––––
–––––∆∆∆
––––––––
––––––––
–––––∆ 0 ∆
––––∆∆∆∆
––––∆∆∆–
––––––––
–––––∆ ––
–––––∆ ––
––––––––
– – – – – – – –
––––––––
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...