Datasheet

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
PWM Channel
Period Registers
(PWMPERx)
There is a dedicated period register for each channel. The value in this
register determines the period of the associated PWM channel.
The period registers for each channel are double buffered so that if they
change while the channel is enabled, the change will NOT take effect
until one of the following occurs:
• The effective period ends
• The counter is written (counter resets to $00)
• The channel is disabled
In this way, the output of the PWM will always be either the old waveform
or the new waveform, not some variation in between. If the channel is
not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
NOTE: Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the
double buffering scheme.
Reference PWM Period and Duty for more information.
To calculate the output period, take the selected clock source period for
the channel of interest (A, B, SA, or SB) and multiply it by the value in
the period register for that channel:
• Left Aligned Output (CAEx=0)
PWMx Period = Channel Clock Period * PWMPERx
• Center Aligned Output (CAEx=1)
PWMx Period = Channel Clock Period * (2 * PWMPERx)
For Boundary Case programming values, please refer to PWM
Boundary Cases.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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