Datasheet

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
These registers are reserved for factory testing of the PWM module and
are not available in normal modes.
Read: always read $00 in normal modes
Write: unimplemented in normal modes
WARNING: Writing to this register when in special modes can alter the PWM
functionality.
PWM Channel
Counter Registers
(PWMCNTx)
Each channel has a dedicated 8-bit up/down counter which runs at the
rate of the selected clock source. The counter can be read at any time
without affecting the count or the operation of the PWM channel. In left
aligned output mode, the counter counts from 0 to the value in the period
register – 1. In center aligned output mode, the counter counts from 0 up
to the value in the period register and then back down to 0.
Any value written to the counter causes the counter to reset to $00, the
counter direction to be set to up, the immediate load of both duty and
period registers with values from the buffers, and the output to change
according to the polarity bit. The counter is also cleared at the end of the
effective period (see Sections Left Aligned Outputs and Center Aligned
Outputs for more details). When the channel is disabled (PWMEx=0),
the PWMCNTx register does not count. When a channel becomes
enabled (PWMEx=1), the associated PWM counter starts at the count in
the PWMCNTx register. For more detailed information on the operation
of the counters, reference PWM Timer Counters.
In concatenated mode, writes to the 16-bit counter by using a 16-bit
access or writes to either the low or high order byte of the counter will
reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency
CAUTION: Writing to the counter while the channel is enabled can cause an
irregular PWM cycle to occur.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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