Datasheet

Pulse Width Modulator (PWM)
Register Descriptions
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
CAE2 — Center Aligned Output Mode on channel 2
1 = Channel 2 operates in Center Aligned Output Mode.
0 = Channel 2 operates in Left Aligned Output Mode.
CAE1 — Center Aligned Output Mode on channel 1
1 = Channel 1 operates in Center Aligned Output Mode.
0 = Channel 1 operates in Left Aligned Output Mode.
CAE0 — Center Aligned Output Mode on channel 0
1 = Channel 0 operates in Center Aligned Output Mode.
0 = Channel 0 operates in Left Aligned Output Mode.
PWM Control
Register (PWMCTL)
The PWMCTL register provides for various control of the PWM module.
Read: anytime
Write: anytime
There are four control bits for concatenation, each of which is used to
concatenate a pair of PWM channels into one 16-bit channel. When
channels 6 and 7 are concatenated, channel 6 registers become the
high order bytes of the double byte channel as shown in Figure 52.
Similarly, when channels 4 and 5 are concatenated, channel 4 registers
become the high order bytes of the double byte channel. When channels
2 and 3 are concatenated, channel 2 registers become the high order
bytes of the double byte channel. When channels 0 and 1 are
concatenated, channel 0 registers become the high order bytes of the
double byte channel.
Reference PWM 16-Bit Functions for a more detailed description of the
concatenation PWM Function.
Address Offset: $0005
Bit 7 6 5 4 3 2 1 Bit 0
Read:
CON67 CON45 CON23 CON01 PSWAI PFRZ
00
Write:
Reset: 0 00000 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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