Datasheet

Central Processing Unit (CPU)
Instruction Set Summary
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
DEC opr16a
DEC oprx0_xysppc
DEC oprx9 , xysppc
DEC oprx16 , xysppc
DEC [D, xysppc ]
DEC [ oprx16 , xysppc ]
DECA
DECB
Decrement M; (M)–1⇒M
Decrement A; (A)–1⇒A
Decrement B; (B)–1⇒B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
73 hh ll
63 xb
63 xb ff
63 xb ee ff
63 xb
63 xb ee ff
43
53
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
DES Decrement SP; (SP)–1⇒SP;
assembles as LEAS –1,SP
IDX 1B 9F Pf
DEX Decrement X; (X)–1⇒X INH 09 O
DEY Decrement Y; (Y)–1⇒Y INH 03 O
EDIV Extended divide, unsigned; 32 by 16 to
16-bit; (Y:D)÷(X)⇒Y; remainder⇒D
INH 11 ffffffffffO
EDIVS Extended divide, signed; 32 by 16 to
16-bit; (Y:D)÷(X)⇒Y; remainder⇒D
INH 18 14 OffffffffffO
EMACS
opr16a Extended multiply and accumulate,
signed; (M
X
:M
X+1
)×(M
Y
:M
Y+1
)+
(M~M+3)⇒M~M+3; 16 by 16 to 32-bit
Special 18 12 hh ll ORROfffRRfWWP
EMAXD
oprx0_xysppc
EMAXD oprx9 , xysppc
EMAXD oprx16 , xysppc
EMAXD [D, xysppc ]
EMAXD [ oprx16 , xysppc ]
Extended maximum in D; put larger of 2
unsigned 16-bit values in D;
MAX[(D), (M:M+1)]⇒D;
N, Z, V, C bits reflect result of internal
compare [(D)–(M:M+1)]
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1A xb
18 1A xb ff
18 1A xb ee ff
18 1A xb
18 1A xb ee ff
ORPf
ORPO
OfRPP
OfIfRPf
OfIPRPf
EMAXM
oprx0_xysppc
EMAXM oprx9 , xysppc
EMAXM oprx16 , xysppc
EMAXM [D, xysppc ]
EMAXM [ oprx16 , xysppc ]
Extended maximum in M; put larger of
2 unsigned 16-bit values in M;
MAX[(D), (M:M+1)]⇒M:M+1;
N, Z, V, C bits reflect result of internal
compare [(D)–(M:M+1)]
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1E xb
18 1E xb ff
18 1E xb ee ff
18 1E xb
18 1E xb ee ff
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
EMIND oprx0_xysppc
EMIND oprx9 , xysppc
EMIND oprx16 , xysppc
EMIND [D, xysppc ]
EMIND [ oprx16 , xysppc ]
Extended minimum in D; put smaller of
2 unsigned 16-bit values in D;
MIN[(D), (M:M+1)]⇒D;
N, Z, V, C bits reflect result of
internal compare [(D)–(M:M+1)]
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1B xb
18 1B xb ff
18 1B xb ee ff
18 1B xb
18 1B xb ee ff
ORPf
ORPO
OfRPP
OfIfRPf
OfIPRPf
EMINM oprx0_xysppc
EMINM oprx9 , xysppc
EMINM oprx16 , xysppc
EMINM [D, xysppc ]
EMINM [ oprx16 , xysppc ]
Extended minimum in M; put smaller of
2 unsigned 16-bit values in M;
MIN[(D), (M:M+1)]⇒M:M+1;
N, Z, V, C bits reflect result of internal
compare [(D)–(M:M+1)]
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18 1F xb
18 1F xb ff
18 1F xb ee ff
18 1F xb
18 1F xb ee ff
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
EMUL Extended multiply, unsigned;
(D)×(Y)⇒Y:D; 16 by 16 to 32-bit
INH 13 ffO
EMULS Extended multiply, signed;
(D)×(Y)⇒Y:D; 16 by 16 to 32-bit
INH 18 13 OfO
OffO (if followed by
page 2 instruction)
EORA # opr8i
EORA opr8a
EORA opr16a
EORA oprx0_xysppc
EORA oprx9 , xysppc
EORA oprx16 , xysppc
EORA [D, xysppc ]
EORA [ oprx16 , xysppc ]
Exclusive OR A; (A)⊕(M)⇒A or
(A)⊕imm⇒A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
88 ii
98 dd
B8 hh ll
A8 xb
A8 xb ff
A8 xb ee ff
A8 xb
A8 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
––––∆∆∆–
––––––––
–––––∆ ––
–––––∆ ––
––––∆∆∆∆
––––∆∆∆∆
––––∆∆∆∆
––––∆∆∆∆
––––∆∆∆∆
––––∆∆∆∆
––––∆∆∆∆
––––∆∆– ∆
––––∆∆– ∆
––––∆∆0–
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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