Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Pulse Width Modulator (PWM)
Register Descriptions
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
PCKA2–PCKA0 — Prescaler Select for Clock A
Clock A is one of two clock sources which can be used for channels
0, 1, 4, or 5. These three bits determine the rate of clock A, as shown
in the following table.
Table 50 Clock B Prescaler Selects
PCKB2 PCKB1 PCKB0
Value of
Clock B
0 0 0 E
0 0 1 E / 2
0 1 0 E / 4
0 1 1 E / 8
1 0 0 E / 16
1 0 1 E / 32
1 1 0 E / 64
1 1 1 E / 128
Table 51 Clock A Prescaler Selects
PCKA2 PCKA1 PCKA0
Value of
Clock A
0 0 0 E
0 0 1 E / 2
0 1 0 E / 4
0 1 1 E / 8
1 0 0 E / 16
1 0 1 E / 32
1 1 0 E / 64
1 1 1 E / 128
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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