Datasheet

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
PCLK2 — Pulse Width Channel 2 Clock Select
1 = Clock SB is the clock source for PWM channel 2.
0 = Clock B is the clock source for PWM channel 2.
PCLK1 — Pulse Width Channel 1 Clock Select
1 = Clock SA is the clock source for PWM channel 1.
0 = Clock A is the clock source for PWM channel 1.
PCLK0 — Pulse Width Channel 0 Clock Select
1 = Clock SA is the clock source for PWM channel 0.
0 = Clock A is the clock source for PWM channel 0.
PWM Prescale
Clock Select
Register
(PWMPRCLK)
This register selects the prescale clock source for clocks A and B
independently.
Read: anytime
Write: anytime
CAUTION: PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a
truncated or stretched pulse can occur during the transition.
PCKB2–PCKB0 — Prescaler Select for Clock B
Clock B is one of two clock sources which can be used for channels
2, 3, 6, or 7. These three bits determine the rate of clock B, as shown
in the following table.
Address Offset: $0003
Bit 7 654321Bit 0
Read: 0
PCKB2 PCKB1 PCKB0
0
PCKA2 PCKA1 PCKA0
Write:
Reset: 00000000
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...