Datasheet

Pulse Width Modulator (PWM)
Register Descriptions
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
PWM Clock Select
Register (PWMCLK)
Each PWM channel has a choice of two clocks to use as the clock
source for that channel as described below.
Read: anytime
Write: anytime
CAUTION: Register bits PCLK0 to PCLK7 can be written anytime. If a clock select
is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
PCLK7 — Pulse Width Channel 7 Clock Select
1 = Clock SB is the clock source for PWM channel 7.
0 = Clock B is the clock source for PWM channel 7.
PCLK6 — Pulse Width Channel 6 Clock Select
1 = Clock SB is the clock source for PWM channel 6.
0 = Clock B is the clock source for PWM channel 6.
PCLK5 — Pulse Width Channel 5 Clock Select
1 = Clock SA is the clock source for PWM channel 5.
0 = Clock A is the clock source for PWM channel 5.
PCLK4 — Pulse Width Channel 4 Clock Select
1 = Clock SA is the clock source for PWM channel 4.
0 = Clock A is the clock source for PWM channel 4.
PCLK3 — Pulse Width Channel 3 Clock Select
1 = Clock SB is the clock source for PWM channel 3.
0 = Clock B is the clock source for PWM channel 3.
Address Offset: $0002
Bit 7 654321Bit 0
Read:
PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
Write:
Reset: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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