Datasheet

Pulse Width Modulator (PWM)
Register Descriptions
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
PWM Polarity
Register (PWMPOL)
The starting polarity of each PWM channel waveform is determined by
the associated PPOLx bit in the PWMPOL register. If the polarity bit is
one, the PWM channel output is high at the beginning of the cycle and
then goes low when the duty count is reached. Conversely, if the polarity
bit is zero, the output starts low and then goes high when the duty count
is reached.
Read: anytime
Write: anytime
CAUTION: PPOLx register bits can be written anytime. If the polarity is changed
while a PWM signal is being generated, a truncated or stretched pulse
can occur during the transition.
PPOL7 — Pulse Width Channel 7 Polarity
1 = PWM channel 7 output is high at the beginning of the period,
then goes low when the duty count is reached.
0 = PWM channel 7 output is low at the beginning of the period,
then goes high when the duty count is reached.
PPOL6 — Pulse Width Channel 6 Polarity
1 = PWM channel 6 output is high at the beginning of the period,
then goes low when the duty count is reached.
0 = PWM channel 6 output is low at the beginning of the period,
then goes high when the duty count is reached.
PPOL5 — Pulse Width Channel 5 Polarity
1 = PWM channel 5 output is high at the beginning of the period,
then goes low when the duty count is reached.
0 = PWM channel 5 output is low at the beginning of the period,
then goes high when the duty count is reached.
Address Offset: $0001
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
Write:
Reset: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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