Datasheet

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
PWME5 — Pulse Width Channel 5 Enable
1 = Pulse Width channel 5 is enabled. The pulse modulated signal
becomes available at PWM, o/p bit 5 when its clock source
begins its next cycle.
0 = Pulse Width channel 5 is disabled.
PWME4 — Pulse Width Channel 4 Enable
1 = Pulse Width channel 4 is enabled. The pulse modulated signal
becomes available at PWM, o/p bit 4 when its clock source
begins its next cycle. If CON45=1, then bit has no effect and
PWM output line4 is disabled.
0 = Pulse Width channel 4 is disabled.
PWME3 — Pulse Width Channel 3 Enable
1 = Pulse Width channel 3 is enabled. The pulse modulated signal
becomes available at PWM, o/p bit 3 when its clock source
begins its next cycle.
0 = Pulse Width channel 3 is disabled.
PWME2 — Pulse Width Channel 2 Enable
1 = Pulse Width channel 2 is enabled. The pulse modulated signal
becomes available at PWM, o/p bit 2 when its clock source
begins its next cycle. If CON23=1, then bit has no effect and
PWM output line2 is disabled.
0 = Pulse Width channel 2 is disabled.
PWME1 — Pulse Width Channel 1 Enable
1 = Pulse Width channel 1 is enabled. The pulse modulated signal
becomes available at PWM, o/p bit 1 when its clock source
begins its next cycle.
0 = Pulse Width channel 1 is disabled.
PWME0 — Pulse Width Channel 0 Enable
1 = Pulse Width channel 0 is enabled. The pulse modulated signal
becomes available at PWM, o/p bit 0 when its clock source
begins its next cycle. If CON01=1, then bit has no effect and
PWM output line0 is disabled.
0 = Pulse Width channel 0 is disabled.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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