Datasheet

Pulse Width Modulator (PWM)
Register Descriptions
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
PWM Enable
Register (PWME)
Each PWM channel has an enable bit (PWMEx) to start its waveform
output. When any of the PWMEx bits are set (PWMEx=1), the
associated PWM output is enabled immediately. However, the actual
PWM waveform is not available on the associated PWM output until its
clock source begins its next cycle due to the synchronization of PWMEx
and the clock source.
The first PWM cycle after enabling the channel can be irregular.
An exception to this is when channels are concatenated. Once
concatenated mode is enabled (CONxx bits set in PWMCTL register)
then enabling/disabling the corresponding 16-bit PWM channel is
controlled by the low order PWMEx bit. In this case, the high order bytes
PWMEx bits have no effect and their corresponding PWM output lines
are disabled.
Read: anytime
Write: anytime
PWME7 — Pulse Width Channel 7 Enable
1 = Pulse Width channel 7 is enabled. The pulse modulated signal
becomes available at PWM output line7 when its clock source
begins its next cycle.
0 = Pulse Width channel 7 is disabled.
PWME6 — Pulse Width Channel 6 Enable
1 = Pulse Width channel 6 is enabled. The pulse modulated signal
becomes available at port PWM output line6 when its clock
source begins its next cycle. If CON67=1, then bit has no effect
and PWM output line6 is disabled.
0 = Pulse Width channel 6 is disabled.
Address Offset: $0000
Bit 7 654321Bit 0
Read:
PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
Write:
Reset: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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