Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Pulse Width Modulator (PWM)
MC9S12DP256 — Revision 1.1
Pulse Width Modulator (PWM)
Register Map
This section describes the content of the registers in the PWM. The base
address of the PWM module is determined at the MCU level when the
MCU is defined. The register decode map is fixed and begins at the first
address of the module address offset. The figure below shows the
registers associated with the PWM and their relative offset from the base
address. The register detail description follows the order they appear in
the register map.
Reserved bits within a register will always read as 0 and the write will be
unimplemented. Unimplemented functions are indicated by shaded bits.
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 BIt 1 Bit 0
Address
Offset
PWME Read:
PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 $0000
Write:
PWMPOL Read:
PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 $0001
Write:
PWMCLK Read:
PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 $0002
Write:
PWMPRCLK Read: 0
PCKB2 PCKB1 PCKB0
0
PCKA2 PCKA1 PCKA0 $0003
Write:
PWMCAE Read:
CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 $0004
Write:
PWMCTL Read:
CON67 CON45 CON23 CON01 PSWAI PFRZ
00
$0005
Write:
PWMTST Read: 0 0 0 00000
$0006
Write:
PWMPRSC Read: 0 0 0 00000
$0007
Write:
PWMSCLA Read:
Bit 7 6 5 4 3 2 1 Bit 0 $0008
Write:
PWMSCLB Read:
Bit 7 6 5 4 3 2 1 Bit 0 $0009
Write:
PWMSCNTA Read: 0 0 0 00000
$000A
Write:
PWMSCNTB Read: 0 0 0 00000
$000B
Write:
= Unimplemented
Figure 45 PWM Register Map
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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