Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Central Processing Unit (CPU)
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
CMPB #
opr8i
CMPB
opr8a
CMPB
opr16a
CMPB
oprx0_xysppc
CMPB
oprx9
,
xysppc
CMPB
oprx16
,
xysppc
CMPB [D,
xysppc
]
CMPB [
oprx16
,
xysppc
]
Compare B; (B)–(M) or (B)–imm IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C1 ii
D1 dd
F1 hh ll
E1 xb
E1 xb ff
E1 xb ee ff
E1 xb
E1 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
COM
opr16a
COM
oprx0_xysppc
COM
oprx9
,
xysppc
COM
oprx16
,
xysppc
COM [D,
xysppc
]
COM [
oprx16
,
xysppc
]
COMA
COMB
Complement M; (M)=$FF–(M)⇒M
Complement A; (A)=$FF–(A)⇒A
Complement B; (B)=$FF–(B)⇒B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
71 hh ll
61 xb
61 xb ff
61 xb ee ff
61 xb
61 xb ee ff
41
51
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
CPD #
opr16i
CPD
opr8a
CPD
opr16a
CPD
oprx0_xysppc
CPD
oprx9
,
xysppc
CPD
oprx16
,
xysppc
CPD [D,
xysppc
]
CPD [
oprx16
,
xysppc
]
Compare D; (A:B)–(M:M+1) or
(A:B)–imm
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8C jj kk
9C dd
BC hh ll
AC xb
AC xb ff
AC xb ee ff
AC xb
AC xb ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
CPS #
opr16i
CPS
opr8a
CPS
opr16a
CPS
oprx0_xysppc
CPS
oprx9,xysppc
CPS
oprx16
,
xysppc
CPS [D,
xysppc
]
CPS [
oprx16
,
xysppc
]
Compare SP; (SP)–(M:M+1) or
(SP)–imm
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8F jj kk
9F dd
BF hh ll
AF xb
AF xb ff
AF xb ee ff
AF xb
AF xb ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
CPX #
opr16i
CPX
opr8a
CPX
opr16a
CPX
oprx0_xysppc
CPX
oprx9
,
xysppc
CPX
oprx16
,
xysppc
CPX [D,
xysppc
]
CPX [
oprx16
,
xysppc
]
Compare X; (X)–(M:M+1) or (X)–imm IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8E jj kk
9E dd
BE hh ll
AE xb
AE xb ff
AE xb ee ff
AE xb
AE xb ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
CPY #
opr16i
CPY
opr8a
CPY
opr16a
CPY
oprx0_xysppc
CPY
oprx9
,
xysppc
CPY
oprx16
,
xysppc
CPY [D,
xysppc
]
CPY [
oprx16
,
xysppc
]
Compare Y; (Y)–(M:M+1) or (Y)–imm IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8D jj kk
9D dd
BD hh ll
AD xb
AD xb ff
AD xb ee ff
AD xb
AD xb ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
DAA Decimal adjust A for BCD INH 18 07 OfO
DBEQ
abdxysp
,
rel9
Decrement and branch if equal to 0;
(counter)–1⇒counter;
if (counter)=0, then branch
REL
(9-bit)
04 lb rr PPP (branch)
PPO (no branch)
DBNE
abdxysp
,
rel9
Decrement and branch if not equal to 0;
(counter)–1⇒counter;
if (counter)≠0, then branch
REL
(9-bit)
04 lb rr PPP (branch)
PPO (no branch)
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
––––∆∆∆∆
––––∆∆01
––––∆∆∆∆
––––∆∆∆∆
––––∆∆∆∆
––––∆∆∆∆
––––∆∆? ∆
––––––––
––––––––
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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