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Clocks and Reset Generator (CRG)
Interrupt Operation
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
Interrupt Vectors The interrupts/reset vectors requested by the CRG are listed below.
Table 49 CRG Interrupt Vectors
Vector Address Interrupt Source
CCR
Mask
Local Enable
HPRIO Value to
Elevate
$FFFF, $FFFE Reset None None
$FFFC, $FFFD crystal monitor reset None PLLCTL (CME)
$FFFA, $FFFB COP watchdog reset None COPCTL (CR[2:0] nonzero)
(1)
Real time interrupt I bit CRGINT (RTIE)
(2)
(3)
LOCK interrupt I bit CRGINT (LOCKIE)
(4)
(5)
SCM interrupt I bit CRGINT (SCMIE)
(6)
1. RTI vector address is specific to MCU, refer to MCU specification.
2. RTI HPRIO value is specific to MCU, refer to MCU specification.
3. LOCK vector address is specific to MCU, refer to MCU specification.
4. LOCK HPRIO value is specific to MCU, refer to MCU specification.
5. SCM vector address is specific to MCU, refer to MCU specification.
6. SCM HPRIO value is specific to MCU, refer to MCU specification.
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