Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
Reset Initialization
When a reset occurs, CRG registers and control bits are changed to
known start-up states, as outlined in Register Descriptions.
Interrupt Operation
Real Time Interrupt The CRG generates a real time interrupt when the selected interrupt
time period elapses. RTI interrupts are locally disabled by setting the
RTIE bit to zero. The real time interrupt flag (RTIF) is set to1 when a
timeout occurs, and is cleared to 0 by a write to 1 to the RTIF bit.
COP (Computer
Operating
Properly)
Watchdog Reset
The device will generate a reset when a COP watchdog failure occurs.
This is locally disabled by setting the COP rate select bits in COPCTL
(CR2,CR1,CR0) to zero.
Crystal Monitor
Reset
The device will generate a reset when a crystal monitor failure occurs.
This is locally disabled by clearing CME bit in PLLCTL register.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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