Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Clocks and Reset Generator (CRG)
External Pin Descriptions
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
Figure 42 Common Crystal Connections
Figure 43 External Oscillator Connections
Reset (RESET) RESET is an active low bidirectional control signal that acts as an input
to initialize the MCU to a known start-up state. It also acts as an
open-drain output to indicate that an internal failure has been detected
in either the crystal monitor or COP watchdog circuit. The MCU goes into
reset asynchronously and comes out of reset synchronously. This allows
the part to reach a proper reset state even if the clocks have failed, while
allowing synchronized operation when starting out of reset. See System
Reset Generator.
MCU
C
EXTAL
XTAL
Crystal or
VSSPLL
ceramic resonator
C
MCU
EXTAL
XTAL
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
NC
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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