Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
External Pin Descriptions
VDDPLL, VSSPLL These pins provide operating voltage and ground for the Phased-Locked
Loop. This allows the supply voltage to the PLL to be bypassed
independently.
XFC A passive external loop filter must be placed on the control line (XFC
pad). The filter is a second-order, low-pass filter to eliminate the VCO
input ripple. The value of the external filter network and the reference
frequency determines the speed of the corrections and the stability of the
PLL.
Figure 41 PLL Loop Filter Connections
EXTAL, XTAL These pins provide the interface for either a crystal or a CMOS
compatible clock to control the internal clock generator circuitry. EXTAL
is the external clock input or the input to the crystal oscillator amplifier.
XTAL is the output of the crystal oscillator amplifier. All the device clocks
are derived from the EXTAL input frequency.
MCU
XFC
R
0
C
s
VDDPLL
C
p
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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