Datasheet

Clocks and Reset Generator (CRG)
Register Descriptions
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
CRG Test Control
Register (CTCTL)
The CTCTL register is reserved for test mode only.:
Read: always read $00 except in test modes.
Write: only in test modes.
CRG COP Timer
Arm/Reset
Register
(ARMCOP)
This register is used to arm and reset the COP time-out.
Always reads $00.
Writing $55 to this address is the first step of the COP watchdog
sequence.
Writing $AA to this address is the second step of the COP watchdog
sequence.
Other instructions may be executed between these writes but both must
be completed in the correct order prior to time-out to avoid a COP reset.
Writing any value (when COP is enabled by setting CR[2:0] nonzero)
other than $55 or $AA causes a COP reset to occur.
Address Offset: $000A
Bit 7 6543210
Read:
TCTL7 TCTL6 TCTL5 TCTL4 TCTL3 TCTL2 TCTL1 TCTL0
Write:
Reset: 00000000
Address Offset: $000E
Bit 7 6543210
Read: 00000000
Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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