Datasheet

Clocks and Reset Generator (CRG)
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
CRG Force and
Bypass Test
Register (FORBYP)
The FORBYP register is reserved for test mode only.:
Read: always read $00 except in test modes.
Write: only in test modes.
Table 48 COP Watchdog Rates
(1)
1. Times are referenced from the previous COP time-out reset (writing $55/$AA to the ARMCOP
register)
CR2 CR1 CR0
Divide
OSCCLK by
Window COP enabled:
Window start
(OSCCLK Periods)
Window
end
OSCCLK Periods)
0 0 0 OFF OFF OFF
001 2
14
12297 16387
010 2
16
49161 65539
011 2
18
196,617 262,147
100 2
20
786,441 1,048,579
101 2
22
3,145,737 4,194,307
110 2
23
6,291,465 8,388,611
111 2
24
12,582,921 16,777,219
Address Offset: $0009
Bit 7 6543210
Read:
RTIBYP COPBYP
0
PLLBYP SCBYP
0
FCM
0
Write:
Reset: 00000000
= Unimplemented or reserved
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Freescale Semiconductor, Inc.
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