Datasheet

Central Processing Unit (CPU)
Instruction Set Summary
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
BPL rel8 Branch if plus; if N=0, then
(PC)+2+rel⇒PC
REL 2A rr PPP (branch)
P (no branch)
BRA rel8 Branch always REL 20 rr PPP
BRCLR
opr8a , msk8 , rel8
BRCLR opr16a , msk8 , rel8
BRCLR oprx0_xysppc , msk8 , rel8
BRCLR oprx9 , xysppc , msk8 , rel8
BRCLR oprx16 , xysppc , msk8 , rel8
Branch if bit(s) clear; if
(M)•(mask byte)=0, then
(PC)+2+rel⇒PC
DIR
EXT
IDX
IDX1
IDX2
4F dd mm rr
1F hh ll mm rr
0F xb mm rr
0F xb ff mm rr
0F xb ee ff mm rr
rPPP
rfPPP
rPPP
rfPPP
PrfPPP
BRN rel8 Branch never REL 21 rr P
BRSET
opr8 , msk8 , rel8
BRSET opr16a , msk8 , rel8
BRSET oprx0_xysppc , msk8 , rel8
BRSET oprx9 , xysppc , msk8 , rel8
BRSET oprx16 , xysppc , msk8 , rel8
Branch if bit(s) set; if
(M)•(mask byte)=0, then
(PC)+2+rel⇒PC
DIR
EXT
IDX
IDX1
IDX2
4E dd mm rr
1E hh ll mm rr
0E xb mm rr
0E xb ff mm rr
0E xb ee ff mm rr
rPPP
rfPPP
rPPP
rfPPP
PrfPPP
BSET opr8 , msk8
BSET opr16a , msk8
BSET oprx0_xysppc , msk8
BSET oprx9 , xysppc , msk8
BSET oprx16 , xysppc , msk8
Set bit(s) in M; (M) | (mask byte)⇒M DIR
EXT
IDX
IDX1
IDX2
4C dd mm
1C hh ll mm
0C xb mm
0C xb ff mm
0C xb ee ff mm
rPwO
rPwP
rPwO
rPwP
frPwPO
BSR rel8 Branch to subroutine; (SP)–2⇒SP;
RTN
H
:RTN
L
⇒M
SP
:M
SP+1
;
(PC)+2+rel⇒PC
REL 07 rr SPPP
BVC
rel8 Branch if V clear; if V=0, then
(PC)+2+rel⇒PC
REL 28 rr PPP (branch)
P (no branch)
BVS
rel8 Branch if V set; if V=1, then
(PC)+2+rel⇒PC
REL 29 rr PPP (branch)
P (no branch)
CALL opr16a , page
CALL oprx0_xysppc , page
CALL oprx9 , xysppc , page
CALL oprx16 , xysppc , page
CALL [D, xysppc ]
CALL [ oprx16 , xysppc ]
Call subroutine in expanded memory;
(SP)–2⇒SP;
RTN
H
:RTN
L
⇒M
SP
:M
SP+1
;
(SP)–1⇒SP; (PPG)⇒M
SP
;
pg⇒PPAGE register;
subroutine address⇒PC
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
4A hh ll pg
4B xb pg
4B xb ff pg
4B xb ee ff pg
4B xb
4B xb ee ff
gnSsPPP
gnSsPPP
gnSsPPP
fgnSsPPP
fIignSsPPP
fIignSsPPP
CBA Compare A to B; (A)–(B) INH 18 17 OO
CLC
Clear C; assembles as ANDCC #$FE IMM 10 FE P
CLI Clear I; assembles as ANDCC #$EF IMM 10 EF P
CLR
opr16a
CLR oprx0_xysppc
CLR oprx9 , xysppc
CLR oprx16 , xysppc
CLR [D, xysppc ]
CLR [ oprx16 , xysppc ]
CLRA
CLRB
Clear M; $00⇒M
Clear A; $00⇒A
Clear B; $00⇒B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
79 hh ll
69 xb
69 xb ff
69 xb ee ff
69 xb
69 xb ee ff
87
C7
PwO
Pw
PwO
PwP
PIfw
PIPw
O
O
CLV Clear V; assembles as ANDCC #$FD IMM 10 FD P
CMPA #
opr8i
CMPA opr8a
CMPA opr16a
CMPA oprx0_xysppc
CMPA oprx9 , xysppc
CMPA oprx16 , xysppc
CMPA [D, xysppc ]
CMPA [ oprx16 , xysppc ]
Compare A; (A)–(M) or (A)–imm IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
81 ii
91 dd
B1 hh ll
A1 xb
A1 xb ff
A1 xb ee ff
A1 xb
A1 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
––––––––
––––––––
––––––––
––––––––
––––––––
––––∆∆0–
––––––––
––––––––
––––––––
––––––––
––––∆∆∆∆
–––––––0
–––0––––
––––0100
––––––0–
––––∆∆∆∆
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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