Datasheet

Clocks and Reset Generator (CRG)
Register Descriptions
MC9S12DP256 — Revision 1.1
Clocks and Reset Generator (CRG)
CRG COP Control
Register (COPCTL)
A description of the COPCTL register follows:.
Read anytime.
Write once in user mode, anytime in test mode. A write to this register
will initialize the COP counter.
WCOP — Window COP mode
0 = Normal COP operation
1 = Window COP operation
When set, a write to the ARMCOP register must occur in the last 25%
of the selected period. A premature write will also reset the part. As
long as all writes occur during this window, $55 can be written as often
as desired. Once $AA is written after the $55, the time-out logic
restarts and the user must wait until the next window before writing to
ARMCOP. Table 48 shows the exact duration of this window for the
seven available COP rates.
CR[2:0] — COP Watchdog Timer Rate select
These bits select the COP time-out rate.
The following equations describe the timeout period as well as the latest
and earliest time for the write to the ARMCOP register.
Address Offset: $0008
Bit 7 6543210
Read:
WCOP
0000
CR2 CR1 CR0
Write:
Reset: 00000000
TimeOut WindowEnd= OscClkPeriod OscClkDivider 3+()⋅=
WindowStart OscClkPeriod 0.75 OscClkDivider⋅()9+()⋅=
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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